Cache Questions

[mindbend]

OK, thanks for the examples. I'm convinced. Here's some more dumb questions.

Where does general RAM play into this and hy isn't the general system RAM in effect a cache?

Consequently, why isn't cache RAM huge, like 16, 64, 512 RAM? I know cache RAM isn't SIMM/DIMM chips (right?), so I guess expense is part of it, but would big giant amounts of cache RAM help to a proportional degree?

Sorry for the continued dumb questions.

[RacerX]

Actually they aren't dumb questions.

First, for a long time you have been able to create a cache in real RAM (see Memory control panel in Classic OS), it was limited by the mother board bus speed and had to deal with traffic from other apps.

The size issue has to do with efficiency. I like the Browser cache as an example here. For Netscape you can decide just how much hard drive space you want for your browser cache. You would think that more is better, but what happens is that after a certain amount (mine is set to 12 MB) the browser is spending as much or more time searching for cached information as it would have taken to just re-download the information again. Processor cache is the same way, where if you can not make effective use of the larger cache, it could kill any speed increase you would think you could get.

[theed]

to RacerX : common misconception. The RAM cache isn't cache for the RAM, that requires special, faster, dedicated hardware; the RAM cache is cache for the Hard Drive, so that when you read from the HD a big chunk of data is held in RAM, in case you happen to want the next couple of bytes in the near future, it's in RAM instead of on the HD. RAM responds in 6 to 60 ns depending on machine, and HD responds in 7 to 12 ms, similar numbers, different orders of magnitude, but L2/L3 cache and RAM cache (control panel) are not related.

I'm mentioning this here, because it may be easier for some to see the advantage of cache if we talk about RAM and Hard Drives because these ore more tangible for many people. Same concept, different location, and L3 cache is meant to respond in .2ns rather than 6ns.

1GHz cycle takes 0.001 ns
1 ms = 1000 ns
1 sec = 1000 ms (in case you needed this)

[RacerX]

posted by theed
to RacerX : common misconception. The RAM cache isn't cache for the RAM, that requires special, faster, dedicated hardware; the RAM cache is cache for the Hard Drive, so that when you read from the HD a big chunk of data is held in RAM, in case you happen to want the next couple of bytes in the near future, it's in RAM instead of on the HD. RAM responds in 6 to 60 ns depending on machine, and HD responds in 7 to 12 ms, similar numbers, different orders of magnitude, but L2/L3 cache and RAM cache (control panel) are not related.

First it is called disk cache (not RAM cache), and I only brought it up to illustrate an example of in-RAM cache techniques, and never said that it was related to the L1/L2/L3 instruction cache (other than the obvious use of the term cache). But it's main use is storing frequently used information in RAM.

Oh, and theed, just for the record, I don't think that browser cache is related to L1/L2/L3 cache either (wouldn't want you misconstrue that example as well).

And if we are going to be picky, I would point out that in your definition of L2, you missed that fact that Apple's current L2 is at processor speed (which is why the G4's 256k L2 cache is so impressive). But that is just if we are getting picky.

[theed]

didn't mean to diss you my brotha. And yeah, looking at the specs, at clock L2 is pretty sweet. I kinda switched explanations half way through thinking about classic 2 level cache implementations and then moving to Apple's current 3 layer caching set.

Out of curiosity though, when your L1 and L2 cache are both at processor speed, is there really any hierarchy to them? Do they become one big cache in effect? Is L2 8 way associative where L1 is flat? I'm baffled by 1GHz L2, it seems to defy the whole concept of L2 ... it's just too fast. :-)

[RacerX]

I was giving you a hard time .

Your definition of L1 stays the same even in the case of the new G4s. But in the case of the L2, instead of half speed we get full speed which is why that 256k is better than 512k in the normal L2 setting. The problem is that 256K at speed is still not equal to 2 MB at half... but you have that space that was left from when the L2 was internalized, so Apple/Motorola added an extra L3 where you would normally see an L2 before. My guess is that the 256K L2 and the 2 MB L3 give the same boost that a normal (half-speed) 3+ MB L2 would give.

I would point out that in some upgrades (and earlier versions of Rhapsody/Mac OS X Server) the L2 cache of the G3 was not active with out a software patch. That would lead me to believe that the L1 is a function of the inner working of the processor, but the L2+ is utilized (organized) by a set of software instruction. That is just a guess though.