it does not only depend on the 32 bit of the G4, it depends on it's instruction set. There are 32 bit processors which can handle several gigabytes of RAM (Xeon. f.e.).
But the pointers used to adress the RAM are too short to adress any further than 1,5 gigabyte. You could change the instruction set - of course - but I am not a CPU designer so I don't know what a huge task that would be (you'd have to increase the register which holds the data pointers for the RAM addressing), but as it was already pointed out, the G5 will have much larger registers (simply because he can know operate on 64 bit per cycle) and thus the data pointer can reach deeper into the RAM to address areas outside of the current 1,5 gig limit.